A microprocessor may interface with one or more of peripheral devices using a peripheral controller which controls a flow of information between the microprocessor and the peripheral devices. Since there may be differences in data rates among the peripheral devices (e.g., between high end peripheral devices, such as a camera, a memory card, a display, etc., and low end peripheral devices, such as a universal asynchronous receiver/transmitter (UART), a synchronous serial protocol (SSP) device, etc.) as well as between the microprocessor and each peripheral device, a buffer, such as first-in-first-out (FIFO), may be used to compensate the data rate mismatch happening in each communication channel.
Thus, a FIFO may be allocated for each communication channel so that the microprocessor and the respective peripheral device can communicate with each other in spite of the mismatch in their data rates. During a transmit operation, the FIFO is used to temporarily store transmit data written by the microprocessor, where the transmit data may be read and transmitted by a peripheral FIFO controller to the respective peripheral device. Likewise, during a receive operation, the FIFO is used to temporarily store receive data from the peripheral device, where the receive data may be read and forwarded by the peripheral FIFO controller to the microprocessor.
However, due to the dedicated nature of the FIFO, the FIFO may be unused as long as the communication channel remains inactive. Furthermore, when there is a heavy traffic occurring for an active channel, the flow of information for the active channel may slow down as the size of the FIFO dedicated for the active channel may not be large enough to handle the heavy traffic while the FIFO for its neighboring inactive channel sits idle.